The invention relates to an integrated semiconductor memory having a multiplicity of memory cells, which, in a first direction parallel to the surface of a semiconductor substrate, are connected in rows to word lines and, in a second direction parallel to the surface of the semiconductor substrate, are connected in rows to bit lines. The invention furthermore relates to a method for fabricating an integrated semiconductor memory.
Integrated semiconductor memories have a memory cell array in which memory cells are disposed in the form of a matrix on the surface of a semiconductor substrate. Each memory cell has at least one transistor by which the respective memory cell can be driven by mutually crossing lines by which the memory state of the memory cell can be read or altered.
Word lines and bit lines are provided for the electrical driving of the selection transistors. In the case of a MOSFET (metal oxide semiconductor field-effect transistor) as the selection transistor, the gate of the transistor is connected to the word line and the source is connected to the bit line. Word lines and bit lines run parallel to the plane surface of the semiconductor substrate and perpendicularly to one another, i.e., they mutually cross one another. The selection transistors of the memory cells are situated at the crossover points of the lines.
In every semiconductor memory, attempts are made to keep the area taken up by an individual memory cell on the semiconductor substrate as small as possible to allow storage of as much information as possible on the substrate area. The area requirement of a memory cell is prescribed firstly by the complexity of the individual memory cell. A memory cell contains at least one selection transistor and a storage capacitor.
The area requirement is furthermore prescribed by the structure width with which microelectronic structures are produced by lithographic exposure processes on the substrate. The structure width is the minimum width of a microelectronic structure, i.e., a trench or a web, which can be reliably fabricated with a prescribed fabrication technology. Because microelectronic structures are formed using lithographically fabricated masks, the area requirement of a memory cell can be specified in numbers of squares with an edge length that corresponds to the structure width. The minimum area of a structure element is, thus, a square having the size of 1 f2 (f represents the structure width in this case).
Finally, the area requirement is determined by the complexity and the construction of the memory cell itself. The area requirement can be optimized through the type of configuration of the selection transistor, of the storage capacitor, and, if appropriate, of further transistors or other constituent parts of the memory cell.
Today""s memory cells require at least an area of 8 f2 on a semiconductor substrate. Such an area is necessary even in the case of a transistor that has only one selection transistor and a storage capacitor because it is necessary to comply with a certain minimum distance from adjacent memory cells, the minimum distance likewise corresponding to the structure width.
It is accordingly an object of the invention to provide an integrated semiconductor memory and fabrication method that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that further reduces the area requirement of a memory cell.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an integrated semiconductor memory, including a semiconductor substrate having a surface, bit lines, word lines, memory cells connected, in a first direction parallel to the surface of the semiconductor substrate, in rows to the word lines and connected, in a second direction parallel to the surface, in rows to the bit lines, two of respective one of word lines and bit lines being disposed as line pairs, each of the line pairs having a buried line running in the semiconductor substrate and an upper line disposed above the buried line, and the upper line of a given line pair connected to one of the memory cells and the lower bit line of the given line pair being connected to another different one of the memory cells.
With the objects of the invention in view, there is also provided an integrated semiconductor memory, including a semiconductor substrate having a surface, bit lines, respective pairs of the bit lines being disposed as bit line pairs, word lines, respective pairs of the word lines being disposed as word line pairs, memory cells connected, in a first direction parallel to the surface of the semiconductor substrate, in rows to the word lines and connected, in a second direction parallel to the surface, in rows to the bit lines, at least one of the word line pairs and the bit line pairs having a buried line running in the semiconductor substrate and an upper line disposed above the buried line, the upper line being connected to one of the memory cells, and the buried line being connected to another different one of the memory cells.
The integrated semiconductor memory by virtue of the fact that in each case two word lines or in each case two bit lines are formed as line pairs including two lines disposed one above the other, each line pair having a buried line running in the semiconductor substrate and an upper line disposed above the buried line and in that in each case different memory cells are connected to the upper line of a line pair then to the lower bit line of the same line pair.
According to the invention, the leads for the selection transistors for the memory cells are not only disposed along the surface of the semiconductor substrate in the form of a matrix, but layering into the substrate is additionally effected in the case of at least one type of leadsxe2x80x94the word lines or the bit lines. In such a case, these layered lines are disposed in the form of line pairs in the substrate, the lower line of which runs in a manner buried in the substrate and is insulated from the overlying line by an insulating layer. The two lines of a line pair are disposed one above the other, i.e., one vertically above the other, for example, in a common trench one above the other or in the same region of the base area of the semiconductor substrate.
As a result, the memory cells can be disposed, at least in one direction, with up to double the memory cell density on the semiconductor substrate. Along the paired lines, the memory cells are alternately connected to the upper line and the buried line, thereby enabling all the memory cells to be contact-connected. The contact connection can also be effected on different sides of the interconnects, for example, toward the right proceeding from the buried lines and toward the left proceeding from the upper lines. The present invention""s configuration of the lines to form line pairs with lines lying one above the other in the depth enables new configurations and construction of memory cells.
In accordance with another feature of the invention, the bit lines are disposed as buried line pairs and the word lines are disposed laterally next to one another. Such a configuration is advantageous if vertical transistors have to be connected to the bit lines. In such a case, source and drain are situated one above the other so that one of the electrodes can be connected to the buried bit line and the other to the upper bit line. Particularly when the source connections of adjacent selection transistors are disposed alternately above and below the gate connection, the bit line pair according to the invention enables contact connection in two different substrate depths.
Preferably, the word lines cross the line pairs of the bit lines in a middle substrate depth between the two bit lines of a line pair. In such an embodiment, the word lines can still be disposed very near the surface in the semiconductor substrate. A bit line, a word line, and a further bit line of the same bit line pair are disposed one after the other from top to bottom at the point of intersection between the trenches for the bit lines and the word lines.
Two alternative embodiments provide for the upper bit lines to run above the monocrystalline crystal lattice of the semiconductor substrate or to be buried above the buried big lines. Accordingly, an upper bit line can be applied or introduced above or into the trench in which the buried bit line is already disposed. Burying the upper bit line, too, has the advantage that the etching-back can be effected without an additional mask because the trench is already patterned.
In accordance with a further feature of the invention, the memory cells are disposed in cell pairs whose first memory cells are connected to upper bit lines and whose second memory cells are connected to lower bit lines. Combining in each case two memory cells can further reduce the area requirement of the memory cells because the memory cells can be alternately connected to the upper and to the lower bit line. Such a contact connection saves a great deal of space.
Preferably, selection transistors respectively of a first and a second memory cell of a cell pair are formed as vertical transistors whose word lines are disposed in a common trench. By virtue of the configuration of two gate contacts of a memory cell pair in a common trench, the gate contacts are at a distance of less than one structure width from one another. By contrast, if they are disposed in different trenches that each have a width of one structure width and are separated from one another by an additional distance of at least likewise one structure width, the area requirement of the memory cells is significantly larger.
Preferably, a deep trench capacitor connected to the transistor of the first memory cell is disposed below the selection transistors of the first and the second memory cell of a cell pair and a capacitor connected to the transistor of the second memory cell is disposed on the semiconductor substrate, in a stacked construction.
In such a case, the selection transistors are alternately connected to storage capacitors in the substrate and storage capacitors on the substrate so that the storage capacitors disposed at two different levels can be disposed with greater density. In such a case, it is possible to have recourse to prior art technologies for fabricating deep trench capacitors that are buried in the substrate and extend far into the depth, and for capacitors of stacked configuration that are formed on the substrate surface.
In accordance with an added feature of the invention, the common trench for the word lines of the first and the second memory cell of a cell pair is preferably disposed above the deep trench capacitor. Because a channel leading into the depth perpendicularly to the substrate surface is already formed for the buried capacitor, the vertical transistors can be disposed in pairs in the upper region of the channel. Their word lines run in pairs in a direction across a multiplicity of capacitors (deep trenches).
Finally, the integrated semiconductor memory can be a DRAM (dynamic random access memory) memory. Memory modules such as DRAMs are those modules that benefit most from space saving because the requirements made of the switching behavior of the memory transistors are less stringent in comparison with logic transistors with partly analog switching functions and memory cells have to be optimized exclusively with regard to reliable charge storage and a small area requirement.
With the objects of the invention in view, there is also provided a method for fabricating an integrated semiconductor memory, including the steps of (a) etching a first trench for word or bit lines into the surface of a semiconductor substrate, (b) forming an electrical insulation layer on the uncovered inner area of the trench, (c) forming a lower electrical line running at the bottom of the trench, (d) filling the trench above the lower line at least up to a part of the as yet unfilled trench depth with an insulating material, and (e) forming an upper electrical line above the lower line on or in the trench.
According to the invention, the trench is filled not with a single line but with two lines that lay one above the other and are insulated from one another in different substrate depths. As a result, it is possible to connect vertical transistors, below the substrate surface, both to their upper and to their lower source and drain contacts, for instance, if the source contacts lie alternately at the top and bottom. The electrical insulation layer electrically insulates the lower line toward the bottom and toward the side and the upper line toward the side.
In accordance with an additional mode of the invention, at the trench, with the aid of a mask, a short connection trench joining the first trench is etched at least as far as a substrate depth, in which the lower line runs, and is filled with a connection contact in the depth. Thus, a bit line buried at the bottom of the trench can be laterally contact-connected if the trench cannot be fabricated at the same time as joining transverse trenches. The connection contacts that are to be introduced into connection trenches can adjoin already doped regions of the selection transistors and, thus, produce the contact between the selection transistor and the buried line.
In accordance with yet another mode of the invention, the connection trench is filled in an insulating manner at least up to a part of the as yet unfilled trench depth above the lower line. Accordingly, the upper line can be introduced into the as yet open region of the trench and, in a similar manner to the lower line, be connected to doped regions of transistors or other electronic devices.
In accordance with a concomitant mode of the invention, after step b), but before step e), a second trench is etched that crosses the first trench in the semiconductor substrate, and two further lines are introduced into the second trench in a substrate depth, which is smaller than the depth of the lower line. The lines running in the second trench are preferably word lines, whereas bit lines run in the first trench. The word lines may likewise be disposed in pairs in the second trench, in which case they are disposed either in the same way as the bit lines at a different depth one above the other or at the same substrate depth next to one another and separated by an insulator. In the latter case, they are led through between the upper and lower bit lines at the crossover point between the first and second trenches. If the word lines are also disposed one above the other, the lower word line can also run below the lower bit line. In such a case, the trench for the word lines must be etched first and the lower word line completed before the trench for the bit line and the lower bit line are produced. Finally, firstly the upper word line and then the upper bit line are produced.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor memory and fabrication method, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.